I ran into this earlier today and was very annoyed at the result, so I thought I'd put this up in the hopes that someone else won't have to go through the same process as I.

On AT91SAM-series processors (in particular I'm using the SAM3N2A), the SPI peripheral supports all four SPI modes (clock idle low/high, shift on rising/falling edge), but the way it's addressed is a little odd. The two bits that control the SPI mode for a slave are the CPOL and NCPHA bits of the appropriate SPI_CSRx register, but the value of the NCPHA bit is the opposite of what you expect. So to set SPI mode 0,0 you use CPOL = 0 and NCPHA = 1.

Otherwise, when you write to a device expecting mode 0,0 everything will be shifted by one bit. I ran into this with a 23LC1024 SRAM chip, where the first byte of each SPI transfer is the opcode, i.e. reading/writing etc. As a result of the shift, the opcode wasn't correct, and so reading returned 0xff for all recieved bytes. Quite annoying.

Hopefully nobody else runs into this, but if you do, perhaps this will help.

Happy hacking!

- ethereal